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Nimbus is a part of a tool set from Exsedia which assists the HDL (VHDL and/or Verilog) designer in constructing large-scale system designs.

Explore your algorithm: Leveraging algorithmic state machines (ASM) as a method of design entry, engineers can capture design intent at an early stage, thus reducing iteration and expediting design closure.

Validate your design: Using a highly intuitive ASM notation, design architectures are graphical so that you and your design team members can speed up analysis time and make better decisions in architectural trade-offs. And because is self-documenting, you can create "easily traceable" documentation, making design management and IP reuse a lot easier.

Verify and simulate: The power of Nimbus' verification feature lies in its design rule checking, which flags design rule violations such as racing conditions and conflict resolutions that may only become apparent during HDL simulation. The static and dynamic verification feature allows you to verify your design for syntax and semantic errors using animation. Nimbus has batch and interactive cycle-based simulation that allows you to generates testbench for subsequent RTL simulation, saving you time in testbench generation.

Generate code:
The code generation engine employs intelligence techniques to produce clear, elegant, optimized Verilog and VHDL codes for industry standard synthesis. High-quality code generation means easier management.

Nimbus also provides an interactive and easy-to-use built-in cycle-based simulator for design verification. This tool even provides a built-in full function wave viewer to view the simulation results. After verification, the design can be translated to various vendor-specific RTL codes for synthesis or event-based simulations. Furthermore, to ensure consistent test-benches for the event based RTL simulators and the built-in cycle-based simulator, the test-benches used for verification within the Nimbus environment can be saved and translated to HDL format.
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