Nimbus is a part of a tool set from Exsedia which assists the HDL (VHDL and/or Verilog) designer in constructing large-scale system designs.

The "correct-by-construction" feature allows the designer to spot errors in the design at the compilation stage (all flowdiagrams need to be compiled prior to simulation and translated to HDL) such as deadlocks, race conditions and unreachable states.

Nimbus also provides an interactive and easy to use built-in cycle-based simulator for design verification. This tool even provides a built-in full function wave viewer to view the simulation results. After verification, the design can be translated to various vendor-specific RTL codes for synthesis or event-based simulations. Furthermore, to ensure consistent test-benches for the event based RTL simulators and the built-in cycle-based simulator, the test-benches used for verification within the Nimbus environment can be saved and translated to HDL format.

Features

• Graphical "select and place" style for behavioral model creation
• Enables manipulation of design hierarchy and concurrent design of control and data path
• Allows architectural explorations
• Built in cycle based simulator with state animation along with a built in full function wave viewer
• HDL test-bench generator
• Selections of Moore and Mealy type machines modeling
• Available on the Sun platforms (Sun OS 5.7, 5.8 or Solaris 7.0 and above with Motif 2.1) and Linux (Red Hat 7.2 or Red Hat 7.3 with Lesstiff 3.5)
• Macro functions and user-defined macro functions for ease of implementation of data-path related functions
• Rule checking for connectivity, signal types, bus resolution, deadlocks and unreachable states.
• Highly optimized translation of behavioral design for vendor specific HDL codes for simulations and synthesis
• Supports embedded memory and cache memory modeling
• Enables complex design functions (multiple clock domains, user defined data path elements and reset schemes)
• Supports prioritization of multiple events/state machines
• Accepts user defined constants and enumerated data types

Major Benefits

• Enables design of datapath and controller concurrently (unlike FSM graphical entry tool)
• Employs high-level expression language (C-like) for shortened learning curves (designer does not need to know HDL syntax to model system behavior)
• Enables the designer to convert algorithms to hardware
• Creates well-structured designs that are easy to modify and reuse
• Enables intuitive and easy visualization of large complex systems
• Improves time to market by minimization the number of iterations of the design cycle
• Creates design documentation to help manage complex designs